Senior DSP Systems & Algorithm Engineer – Space & Defense Payloads
Our dedicated Aerospace & Defense Technology Search Practice has been exclusively retained by a premier designer and manufacturer of high-reliability flight payloads, next-generation radar systems, and resilient satellite communications based in Irvine, California. We are searching for an accomplished Digital Signal Processing (DSP) Engineer to drive the design, algorithmic modeling, simulation, and hardware-adjacent implementation of mission-critical processing pipelines for low Earth orbit (LEO) constellations, airborne radar, and electronic warfare (EW) systems.
The Southern California Aerospace Corridor Context
Positioned at the epicenter of Orange County’s thriving aerospace cluster—with direct technical links to Los Angeles Space Beach developments, Space Systems Command (SSC) programs in El Segundo, and the naval testing corridors of Point Mugu and China Lake—this role puts you at the absolute vanguard of defense modernization. You will lead the transition of advanced waveforms from mathematical concepts into hardened, low-latency embedded architectures engineered to operate reliably under extreme space radiation and contested electromagnetic conditions.
Core Engineering Responsibilities
As the technical anchor for payload signal chains, your contributions span the entire product life cycle from conceptual mathematical derivation to flight-unit RF chamber characterization:
- Architect, model, and simulate complex DSP algorithms in MATLAB, Simulink, and Python for direct-conversion and heterodyne RF transceivers.
- Execute high-fidelity floating-point to fixed-point signal conversions, rigorously analyzing dynamic range, bit growth, quantization noise, and Signal-to-Quantization-Noise Ratio (SQNR).
- Collaborate closely with FPGA design teams to map high-throughput streaming algorithms onto multi-tile AMD/Xilinx Zynq UltraScale+ RFSoC and Kintex UltraScale architectures via AXI4-Stream interfaces.
- Formulate adaptive beamforming weights, sidelobe cancellation routines, and Space-Time Adaptive Processing (STAP) schemes for multi-element phased array antennas.
- Design, calibrate, and validate digital pre-distortion (DPD), IQ imbalance compensation, Direct Digital Synthesis (DDS), and Numerically Controlled Oscillator (NCO) cores.
- Conduct hardware-in-the-loop (HIL) validation using modern lab instrumentation, including high-speed real-time oscilloscopes, vector signal generators, and spectrum analyzers.
Mathematical Modeling and Algorithm Prototyping
You will be responsible for defining the theoretical baseline for complex modulation, channelization, and detection algorithms. This includes deriving custom multi-rate polyphase decimation and interpolation filter banks, matched filter estimators, and pulse compression networks configured for Linear Frequency Modulation (LFM) and non-linear phase-coded radar waveforms.
Hardware Realization and High-Speed Pipeline Translation
Working at the boundary between mathematical signal theory and physical digital logic, you will translate theoretical architectures into low-latency, parallel execution paths optimized for modern heterogeneous System-on-Chip platforms.
Waveform Generation & Transceiver DSP Subsystems
You will oversee the end-to-end transceiver processing pipeline, ensuring that Digital Down-Conversion (DDC) and Digital Up-Conversion (DUC) blocks maintain absolute spectral purity, low phase noise, and negligible group delay distortion across multiple gigahertz of instantaneous bandwidth.
Low-Latency Anti-Jamming & Pulse Compression Processing
You will engineer real-time interference mitigation pipelines, employing fast spectral analysis, notch-filtering algorithms, and custom adaptive filter topologies capable of defeating active electronic countermeasure (ECM) threats with microsecond-level convergence times.
Technical Stack and Domain Standards
The engineering environment balances agile algorithmic exploration with stringent, flight-rated mission assurance protocols:
- Modeling & Simulation: MATLAB, Simulink, fixed-point designer, Python (NumPy, SciPy), C/C++ (C17/C++20).
- Target Hardware Architectures: AMD/Xilinx Zynq UltraScale+ RFSoC (e.g., ZU29DR, ZU49DR), Versal AI Core, Kintex UltraScale+, Microchip PolarFire.
- Digital Protocols & Streaming: VITA 49.2 (VRT), OpenVPX (VITA 65), SOSA-aligned architectures, AXI4-Stream, JESD204B/C serial interfaces.
- Modulation & Coding Schemes: DVB-S2X, APSK, QAM, BPSK/QPSK spread-spectrum, LDPC, Turbo codes, Reed-Solomon, Viterbi decoders.
- Instrumentation: Keysight N5182B Signal Generators, Rohde & Schwarz FSW Signal and Spectrum Analyzers, Keysight Infiniium High-Bandwidth Oscilloscopes.
Prime Contractor and Stakeholder Engagement
In addition to hands-on analytical execution, you will serve as a key technical subject matter expert during inter-organizational reviews. You will prepare and present rigorous DSP performance analyses at Preliminary Design Reviews (PDR) and Critical Design Reviews (CDR) for prime defense contractors, national security agencies, and commercial space payload operators. You will author clear Interface Control Documents (ICDs) and algorithmic specification packets that facilitate seamless integration across firmware, software, and systems engineering teams.
Candidate Profile & Qualifications
Minimum Requirements
- Bachelor of Science in Electrical Engineering (BSEE), Computer Engineering, or Applied Mathematics with an emphasis on Signal Processing.
- A minimum of five years of professional post-graduate experience delivering digital signal processing designs for aerospace, defense, radar, EW, or satellite communications applications.
- Demonstrated proficiency in MATLAB-based DSP simulation, floating-to-fixed point conversion, and FIR/IIR filter design.
- Deep familiarity with multi-rate signal processing, fast Fourier transforms (FFTs), pulse compression, digital beamforming, and digital modulation standards.
- United States citizenship is strictly required due to ITAR restrictions, export controls, and facility clearance protocols.
Preferred Qualifications
- Master of Science (MSEE) or Ph.D. with dedicated research focus in statistical signal processing, array processing, or modern radar systems.
- Hands-on experience targeting RFSoC platforms, with practical understanding of high-speed ADC/DAC calibration and DSP/FPGA co-design.
- Familiarity with DO-254 or military mission assurance standards for spaceflight-qualified digital hardware.
- Active or recent DoD Secret, Top Secret, or TS/SCI security clearance.
Key Performance Measures & 12-Month Milestones
Your success in this position will be evaluated through concrete, measurable milestones over your first year:
- Month 3: Assume technical ownership of the primary transceiver MATLAB signal chain model and complete a full SQNR and fixed-point budget analysis for an in-flight mission proposal.
- Month 6: Deliver verified fixed-point C++/VHDL co-simulation test vectors for a wideband channelizer pipeline, validating bit-true parity against prototype models.
- Month 12: Successfully support the system-level hardware-in-the-loop integration and RF range testing of a multi-beam phased array payload prototype, meeting all spectral compliance and latency objectives.
Compensation, Cleared Benefits & Working Environment
This is a full-time, direct-hire position based at a state-of-the-art engineering and manufacturing facility in Irvine, CA, operating under a standard 9/80 work schedule (offering every other Friday off). The position offers a highly competitive base salary ranging from $150,000 to $195,000 per annum, commensurate with technical depth, educational background, and security clearance status.
The total rewards package includes a comprehensive medical, dental, and vision program with low employee premiums, an immediate 6% employer match on 401(k) retirement contributions, an annual performance-based incentive bonus, full relocation assistance for non-local candidates, and dedicated annual funding for professional development, publications, and conference attendance.
Application and Confidential Review Process
To initiate a confidential exploration of this role, submit your resume detailing your relevant project history, algorithm modeling experience, and clearance status through our defense practice portal. Qualified engineers will participate in an initial technical screening conversation with our lead aerospace practice partner, followed by a formal interview sequence with the client engineering leadership team.